FIG. 24 represents a connection between a power switching element for constructing a conventional power converting apparatus, and a control IC for driving/controlling this power switching element. In this drawing, reference numerals 1 to 4 show DC power supplies, reference numeral 5 indicates a resistor, reference numeral 6 represents a reactor, reference numerals 7 and 8 show switches, reference numerals 9 and 10 denote diodes, reference numeral 11 and 12 show resistors, and reference numeral 13 denotes an IC for driving the above-described switches 7 and 8.
The above-explained power supplies 1 and 2 are such power supplies for supplying energy to a load constituted by the above-described resistor 5 and the above-explained reactor 6. The power supply 3 is such a power supply for supplying electric power between a VB-terminal and a VS-terminal, corresponding to power supply terminals of the IC 13 for driving the switch 7. The DC power supply 4 is such a power supply for supplying electric power between a VCC-terminal and a COM-terminal of the IC 13 for driving the switch 8. The above-explained resistors 11 and 12 are drive resistors for driving the switches 7 and 8.
A signal HIN and a signal LIN, corresponding to the respective switches 7 and 8, are inputted to the IC 13. When the above signal HIN is "high", an output HO of the IC 13 becomes "high". When the above signal HIN is "low", an output LO of the IC 13 becomes "low". Similarly, when the above signal LIN is "high", an output LO of the IC 13 becomes "high". When the above signal LIN is "low", an output LO of the IC 13 becomes "low".
Also, in FIG. 24, it is now that a voltage applied to a load constructed of the resistor 5 and the resistor 6 is "VL"; a current flowing through the load is "IL"; a voltage applied between the VS terminal and the COM terminal in the IC 13 is "Vrev"; a current flowing through a wiring line used to connect an emitter of the switch 8 and the COM terminal of the IC 13 is "Irev"; and voltages of the DC power supply 1 and of the DC power supply 2 are "E". It should be noted that plus polarities of the respective voltages and the respective currents are directed, as viewed in FIG. 24.
Next, a description will now be made of a power supplying method to the load with reference to FIG. 24 and FIG. 25. At this time, it is assumed that the above-described load current IL is directed to a plus direction. In FIG. 25, (a) shows an operation of the switch 7; (b) indicates an operation of the switch 8; (c) represents a waveform of the load voltage VL; (d) shows a waveform of the load current IL; (e) represents a waveform of a current flowing through the switch 7; and (f) indicates a waveform of a current flowing through the diode 10.
In the drawings, when the switch 7 is turned OFF and the switch 8 is turned ON, the load voltage becomes "-E", and then the magnitude of the load current IL is decreased. In this case, the above-described load current IL actually does not flow through the switch 8, but flows through the diode 10. Next, when the switch 7 is turned ON and the switch 8 is turned OFF, the load voltage becomes +E. The magnitude of the load current IL is increased. At this time, the load current IL flows through the switch 7. In other words, when the ON/OFF controls of the switches 7 and 8 are carried out, the load voltage VL can be controlled, and therefore the above-explained load current IL can be controlled.
Also, FIG. 26 shows an internal circuit of the above-described IC 13. In this drawing, reference number 21 shows a rising edge detecting circuit for detecting a rising edge of the above-described signal HIN, reference numeral 22 indicates a falling edge detecting circuit for detecting a falling edge of the signal HIN, and reference numeral 23 represents an MOSFET which is turned ON when an output of the rising edge detecting circuit 21 is high, and which is turned OFF when the output of the falling edge detecting circuit 21 is low. Reference numeral 24 represents a MOSFET which is turned ON when an output of the rising edge detecting circuit 22 is high, and which is turned OFF when the output of the falling edge detecting circuit 21 is low. Reference numerals 25 and 26 are parasitic diodes of the above-described MOSFET 23 and MOSFET 24, reference numerals 27 and 28 show resistors, reference numerals 29 and 30 indicate zener diodes, reference numeral 31 denotes a flip-flop, and reference numerals 32 and 33 are buffer amplifiers for outputting the above-described signals HO and LO. The zener diodes 29 and 30 are connected so as to protect overvoltage on the input side of the flip-flop 31.
Next, operations of the above-explained IC 13 will now be explained with reference to FIG. 27. In FIG. 27, (a) shows a waveform of the above-explained signal HIN; (b) indicates a waveform of the above-described signal LIN; (c) represents an output waveform of the rising edge detecting circuit 21; (d) shows an output waveform of the falling edge detecting circuit 22; (e) indicates an S-input waveform of the flip-flop 31; (f) represents an R-input waveform of the flip-flop 31; (g) shows a waveform of the output Q of the flip-flop 31; (h) denotes a waveform of the signal HO; and (i) denotes a waveform of the signal LO. The signal LIN is directly outputted via the buffer amplifier 33 as the above-explained signal LO.
First, a description will now be made of a time instant "t1" when the above-explained signal HIN is transferred from "low" to "high". At this time, the output waveform of the rising edge detecting circuit 21 becomes high during a predetermined time period, so that the MOSFET 23 is turned ON.
As a result, since the current flows through the resistor 27, a voltage drop occurs at the resistor 27, and the S-input of the flip-flop 31 becomes "low". Then, the flip-flop 31 is set, so that the signal Q becomes "high".
Next, a description will now be made of a time instant "t2" when the above-explained signal HIN is transferred from "high" to "low". At this time, the output waveform of the rising edge detecting circuit 22 becomes high during a predetermined time period, so that the MOSFET 24 is turned ON.
As a result, since the current flows through the resistor 28, a voltage drop occurs at the resistor 28, and the R-input of the flip-flop 31 becomes "low". Then, the flip-flop 31 is reset, so that the signal Q becomes "low".
Since the signal Q is directly outputted via the buffer amplifier 32 as the signal HO, both the above-described signal HIN and signal HO are made substantially coincident with each other.
The above-explained conventional power converting apparatus has such a merit that since the circuit becomes non-insulating conditions from the signal HIN up to the signal HO and from the signal LIN up to the signal LO, the signal transfer delay is small, as compared with the signal transfer via the electric insulation by the photocoupler and the like, and therefore the signal can be more accurately transferred.
Next, with reference to FIG. 28 to FIG. 30, a description will now be made of operations when the above-described load current IL is commutated from the switch 7 to the diode 10. In FIG. 28, it is now assumed that a current flowing through the switch 7 is "IL1". In FIG. 29, reference numerals 40 to 42 indicate wiring line inductance. It is also assumed that a current flowing through the diode 10 is "IL2". Also, in FIG. 30, (a) shows a waveform of the above-described current IL1; (b) represents a waveform of the above-explained current IL2; and (c) represents a waveform of the above-explained voltage Vrev. In a time period shown in FIG. 30, the above-explained current IL is substantially constant. As indicated in FIG. 28, firstly, the switch 7 is turned ON and the switch 8 is turned OFF. Thus, it is assumed that the above-described load current IL flows via the switch 7.
Next, at the time instant t1, if an OFF-instruction is given to the switch 7 and an ON-instruction is given to the switch 8, then the current IL1 is gradually reduced, as indicated in FIG. 30. At a time instant t2, this current IL1 becomes zero. Also, the current IL2 is gradually increased, and then becomes IL at the time instant t2. At this time, IL=IL1+IL2 can be established.
During the above-described commutation operation, a voltage is produced in direct proportional to an inclination of a current directed, as view in the drawing, in the above-described wiring inductance 40 to 42. At the same time, a drop voltage along a forward direction is produced in the diode 10. A summation of these voltages appears as the above-described voltage Vrev. A waveform of this voltage Vref is schematically shown in FIG. 30(c).
Also, in FIG. 31, to achieve a withstanding voltage in the IC 13, the above-described terminal VB is separated from the above-explained terminal COM by a PN junction. In other words, a parasitic diode 50 is present. As a consequence, when the voltage Vrev becomes negative and the magnitude of this voltage exceeds the voltage V3 of the DC power supply 3, the above-explained parasitic diode 50 is turned ON. A current flows through the COM terminal--the parasitic diode 50--the VB terminal--the DC power supply 3, and the wiring line impedance of the path. When the magnitude of the voltage Vrev is lower than the voltage V3 of the DC power supply 3, a reverse current flows through the parasitic diode 50, and thereafter this parasitic diode 50 is turned OFF. At this stage, waveforms are schematically indicated in FIG. 32. FIG. 32(a) shows the voltage Vrev, and FIG. 32(b) represents the current Irev. As a consequence, a current as indicated in FIG. 32(b) will flow inside the IC 13.
Also, the buffer amplifier 32 is arranged as shown in FIG. 33. In other words, reference numeral 52 shows a p type MOSFET, and reference numeral 53 indicates an n type MOSFET. Two MOSFETs 52 and 53 constitute a so-called "CMOS structure".
When the above-explained CMOS structure is rewritten into a semiconductor structural diagram, such a semiconductor structural diagram is made as shown in FIG. 34. Assuming now that an n-type substrate is used as a substrate, a p well is employed while an n type MOSFET is fabricated. In this structure, a transistor 62 and another transistor 63 are parasitically present. Also, a resistor 60 and another resistor 61 are parasitically present on the substrate.
It is now assumed that a current may flow from the VB terminal into the n-type substrate. At this time, at the resistor 60, a voltage drop appears along a direction of "+" and "-", as indicated in this drawing, so that the above-explained transistor 62 is turned ON. As a result, a current flows from the VB-terminal via the resistor 61 to the VS-terminal, so that a voltage drop appears at the resistor 61 along a direction of "+" and "-", as shown in this drawing, and then the transistor 63 is turned ON. As a consequence, since both the VB-terminal and the VS-terminal shortcircuit the DC power supply 3 via the two turned-ON transistors, not only the erroneous operation of the CMOS structure occurs, but also this CMOS structure is thermally destroyed by the overcurrent. That is, a latch-up phenomenon happens to occur.
When the above-described current Irev is sufficiently large, this may cause the above-mentioned latch-up phenomenon. There is a problem that the IC 13 is erroneously operated, or is electrically destroyed.
Also, when the magnitude of the IC 13 is higher than the voltage V3 of the DC power supply 3, the above-described current Irev may flow through the COM-terminal--diode 25--the zener diode 29--the VB-terminal--the DC power supply 3, and the wiring line impedance of the signal path.
Referring now to FIG. 35, operations when the above current may flow will be explained. In FIG. 35, (a) shows a waveform of the current Irev; (b) indicates a waveform of a current flowing through the diode 25; (c) represents a waveform of a current flowing through the diode 29; and (d) shows a waveform of an S-input of the flip-flop 31.
When the voltage Vrev is lower than the voltage VB of the DC power supply 3 at the time instant t1, since the diode 25 and the zener diode 29 are turned OFF, the circuit operation is entered into the reverse recovery operation, so that minus currents will flow through the respective diodes, as represented in this drawing. At this time, as to the electric charge amount for the reverse recovery, if the change amount of the diode 25 is larger than that of the zener diode 29, as shown in this drawing, the zener diode 29 accomplishes the reverse recovery operation at the time instant t2, and then is turned OFF. Since the diode 25 is still under reverse recovery operation, the minus current continuously flows. Thereafter, at a time instant t3, the reverse recovery operation of the diode 25 is completed and this diode 25 is turned OFF.
At this time, the minus current flowing through the diode 25 will flow through the resistor 27. As a consequence, the S-input waveform of the flip-flop 31 becomes low, as shown in the drawing. Therefore, there is a problem that the output signal of the flip-flop 31 is transferred from a "low" state to a "high" state, and this flip-flop 31 is erroneously ignited.
In other words, as shown in FIG. 36, the above-described current Irev may cause a problem, which flows when the high voltage Vrev is produced along the minus direction.
To solve this problem, as indicated in FIG. 37, in the conventional power converting apparatus, the resistor 70 is connected to the resistor 71, and it is so set: the value of resistor 11=the value of resistor 70+the value of resistor 71 in order to increase the impedance of the signal path through which the current Irev flows. As a result, since the above-described current Irev can be suppressed, it is possible to suppress the erroneous operation and the electric destruction of the IC 13.
Also, in another conventional power converting apparatus, as indicated in FIG. 38, since the diode 72 is connected between the COM terminal and the VS terminal of the IC 13, the current Irev is bypassed by the diode 72, so that the current flowing through the IC 13 can be suppressed. Thus, it is possible to suppress the erroneous operation and the electric destruction of the IC 13.
However, generally speaking, in FIG. 37, in such a case that the switch 7 is selected as a switch element having a large capacity, since the drive resistance value for driving the switch 7 is set to a small resistance value, the resistance value of the resistor 71 must be set to a small value. Thus, there is a problem that such an impedance capable of suppressing the above-described current Irev cannot be obtained.
Also, in FIG. 38, since the current Irev is shunted based upon a ratio of the impedance of the signal path passing through the diode 72 to the impedance of the signal path passing through the IC 13, there are some cases that the current flowing through the IC 13 cannot be completely suppressed, depending upon the characteristic and the connecting way of the diode 72. Also, since the anode and the cathode of the above-described diode 72 are connected to the emitter of the switch 8 and the emitter of the switch 7, when the voltages of the above-described DC power supply 1 and DC power supply 2 are high, the withstanding voltage of the diode 72 must be selected to be a high withstanding voltage in connection with these high voltages. As a consequence, there is another problem that the reliability is deteriorated, and the cost is increased.